Kyle Juretus presented “Reduced Overhead Gate Level Logic Encryption” and Prof. Ioannis Savidis presented “Load Balanced On-Chip Power Delivery for Average Current Demand” at the 2016 Great Lakes Symposium on Very Large Scale Integration (GLSVLSI).
Two ICE Lab papers were presented at the Government Microcircuit Applications & Critical Technology Conference in Orlando Florida held on March 14-17, 2016:
1) Kyle Juretus and Ioannis Savidis, “Low Overhead Gate Level Logic Encryption.”
Abstract: Untrusted third-parties in the IC design flow have raised serious security and reliability concerns. An area of research aimed at ensuring secure and reliable ICs for critical applications is logic encryption, however current implementations incur high per-gate overheads. This paper focuses on gate level logic encryption, with the goal of substantially reducing the per-gate overhead of implementing the encrypted logic.
2) Shazzad Hossain and Ioannis Savidis, “Dynamic Current Mode Inverter for Ultra-Low Power Near-Threshold Computing.”
Abstract: Near-threshold computing (NTC) is a promising technique for low power computation with improved performance per watt. In this paper, three novel differential inverters are proposed that operating at near-threshold voltages. Characterization of the proposed inverters indicates improvements over CMOS and CML with regard to power, performance, and robustness, with a minor cost in area.