Publications

Google Scholar Profile:  Ioannis Savidis

Tutorials

  1. I. Savidis, Emerging ML-AI Techniques for Analog EDA, 2023 IEEE International Symposium on Circuits and Systems, Monterrey, California, May 2023.

Book

  1. V. Pavlidis, I. Savidis and E. G. Friedman, Three-Dimensional Integrated Circuit Design, 2nd Edition , Morgan Kaufmann Publishers, pp. 1-768, 2017, ISBN # 978-0-12-410484-6.

Book Chapter

  1. I. Savidis and E. G. Friedman, “Physical Design Trends for Interconnects,” On-Chip Communication Architectures System on Chip Interconnect , S. Pasricha and N. Dutt, Morgan Kaufmann Publishers, Elsevier, Chapter 11, pp. 403-437, 2008, ISBN # 978-0-12-373892-9.

Dissertations

  1. M. S. Hossain, Power Management Techniques for Ultra-low Voltage Integrated Circuits, Ph.D. Dissertation, Drexel University, November 2021.
  2. K. Juretus, Enhancing the Cybersecurity Root of Trust Through Hardware Layer Logic Obfuscation, Ph.D. Dissertation, Drexel University, July 2020.
  3. D. Pathak, SMART Grid On Chip: Infusing intelligence to on-chip energy management, Ph.D. Dissertation, Drexel University, November 2018.
  4. I. Savidis, Characterization and Modeling of TSV Based 3-D Integrated Circuits, Ph.D. Dissertation, University of Rochester, August 2013.

Journal Papers

  1. V. V. Rao and I. Savidis, “Performance and Security Analysis of Parameter-Obfuscated Analog Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 29, No. 12, pp. 2013 – 2026, December 2021.
  2. M. S. Hossain and I. Savidis, “Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems , Vol. 11, No. 4, pp. 762 – 775, December 2021.
  3. K. Juretus and I. Savidis, “Synthesis of Hidden State Transitions for Sequential Logic Locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Vol. 40, No. 1, pp. 11 – 23, January 2021.
  4. K. Juretus and I. Savidis, “Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Vol. 40, No. 1, pp. 38 – 51, January 2021.
  5. M. Jacovic, K. Juretus, N. Kandasamy, I. Savidis, and K. R. Dandekar “Physical Layer Encryption for Wireless OFDM Communication Systems,” Journal of Hardware and Systems Security , Vol. 4, No. 3, pp. 230 – 245, September 2020.
  6. M. S. Hossain and I. Savidis, “Dynamic Differential Signaling Based Logic Families for Robust Ultra-low Power Near-threshold Computing,” Microelectronics Journal , Vol. 102, No. 9, pp. 1 – 14, August 2020.
  7. K. Juretus and I. Savidis, “Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Vol. 39, No. 8, pp. 1607 – 1620, August 2020.
  8. M. S. Hossain and I. Savidis, “Recycling of Unused Leakage Current for Energy Efficient Multi-voltage Systems,” Microelectronics Journal , Vol. 101, No. 7, pp. 1 – 16, July 2020.
  9. J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. R. Dandekar “Securing Wireless Communication via Hardware-based Packet Obfuscation,” Journal of Hardware and Systems Security , Vol. 3, No. 3, pp. 261 – 272, May 2019.
  10. D. Pathak and I. Savidis, “On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 26, No. 11, pp. 2230 – 2240, November 2018.
  11. M. K. Tavana, M. H. Hajkazemi, D. Pathak, I. Savidis, and H. Homayoun, “ElasticCore: A Dynamic Heterogeneous Platform with Joint Core and Voltage/Frequency Scaling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol.  26, No. 2, pp. 249 – 261, February 2018.
  12. D. Pathak, H. Homayoun, and I. Savidis, “Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 25, No. 9, pp. 2538 – 2551, September 2017.
  13. I. Savidis, B. Ciftcioglu, J. Xu, J. Hu, M. Jain, R. Berman, J. Xue, P. Liu, D. Moore, G. Wicks, M. Huang, H. Wu, and E. G. Friedman, “Heterogeneous 3-D Circuits: Integrating Free-Space Optics with CMOS,” Microelectronics Journal , Vol. 50, No. 4, pp. 66 – 75, April 2016.
  14. I. Savidis, B. Vaisband, and E. G. Friedman, “Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 23, No. 10, pp. 2077 – 2089, October 2015.
  15. I. Savidis, S. Kose, and E. G. Friedman, “Power Noise in TSV-Based 3-D Integrated Circuits,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 2, February 2013.
  16. B. Ciftcioglu , R. Berman, S. Wang, J. Hu, I. Savidis, M. Jain, D. Moore, M. Huang, E. G. Friedman, G. Wicks, and H. Wu, “3-D Integrated Heterogeneous Intra-Chip Free-Space Optical Interconnect,” Optics Express , Vol. 20, No. 4, pp. 4331-4345, February 2012.
  17. V. Pavlidis, I. Savidis, and E. G. Friedman, “Clock Distribution Networks in 3-D Integrated Systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 19, No. 12, pp. 2256-2266, December 2011.
  18. J. Wang, I. Savidis, and E. G. Friedman, “Thermal Analysis of Oxide-Confined VCSEL Arrays,” Microelectronics Journal , Vol. 42, No. 5, pp. 820-825, May 2011.
  19. B. Ciftcioglu, R. Berman, J. Zhang, Z. Darling, S. Wang, J. Hu, J. Xue, A. Garg, M. Jain, I. Savidis, D. Moore, M. Huang, E. G. Friedman, G. Wicks, and H. Wu, “A 3-D Integrated Intra-Chip Free-Space Optical Interconnect for Many-Core Chips,” IEEE Photonics Technology Letters , Vol. 23, No. 3, pp. 164-166, February 2011.
  20. I. Savidis, S. M. Alam, A. Jain, S. Pozder , R. E. Jones, and R. Chatterjee, “Electrical Modeling and Characterization of Through-Silicon vias (TSVs) for 3-D Integrated Circuits,” Microelectronics Journal , Vol. 41, No. 1, pp. 9-16, January 2010.
  21. I. Savidis and E. G. Friedman, “Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance,” IEEE Transactions on Electron Devices , Vol. 56, No. 9, pp. 1873-1881, September 2009.

Conference Papers

  1. V. V. Rao, A. Sasan, and I. Savidis, “Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits,” Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp. 387 – 393, April 2022.
  2. A. Mirzaeian, Z. Tian, S. Manoj, B. S. Latibari, I. Savidis, H. Homayoun, and Avesta Sasan, “Adaptive-Gravity: A Defense Against Adversarial Samples” Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp. 96 – 101, April 2022.
  3. Z. Chen and I. Savidis, “Implementation of Analog Systems on a Reconfigurable Array,“ Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), pp. 1 – 6, March 2022.
  4. Z. Chen and I. Savidis, “Reconfigurable Array for Analog Applications,” Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 361 – 365, November 2021. (presentation video)
  5. Z. Wu and I. Savidis, “Variation-aware Analog Circuit Sizing with Classifier Chains” Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), pp. 1 – 6, September 2021. (presentation video)
  6. M. S. Hossain and I. Savidis, “Energy Efficient Computing with Heterogeneous DNN Accelerators,” Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 1-4, June 2021. (presentation video)
  7. S. Phatharodom, A. Sasan, and I. Savidis, “SAT-attack Resilience Measure for Access Restricted Circuits,” Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 213 – 220, June 2021. (presentation video)
  8. S. A. Beheshti, A. Vakil, S. Manoj, I. Savidis, H. Homayoun, and A. Sasan, “A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop,” Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 181 – 187, June 2021. (presentation video)
  9. Z. Wu and I. Savidis, “CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing,” Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), pp. 49 – 54, November 2020. (presentation video)
  10. V. V. Rao, K. Juretus, and I. Savidis, “Security Vulnerabilities of Obfuscated Analog Circuits,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1 – 5, October 2020. (presentation video)
  11. K. Juretus and I. Savidis, “Reducing Logic Locking Key Leakage Through the Scan Chain,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1 – 5, October 2020. (presentation video)
  12. S. Phatharodom, N. Kandasamy, and I. Savidis, “Modeling SAT-attack Search Complexity,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1 – 5, October 2020. (presentation video)
  13. M. S. Hossain and I. Savidis, “Dynamic Idle Core Management and Leakage Current Reuse in MPSoC Platforms,” Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 49 – 54, August 2020.
  14. S. Phatharodom, N. Kandasamy, and I. Savidis, “Closed-form Estimation of SAT-Attack Resilience,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), pp. 1 – 6, March 2020.
  15. V. V. Rao and I. Savidis, “Multi-Objective Simulation-based Optimization of Analog Transistor Sizing,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), pp. 1 – 6, March 2020.
  16. D. Pathak and I. Savidis, “Applying Swarm Intelligence to Distributed On-Chip Power Management,” Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 532 – 540, November 2019.
  17. D. Pathak and I. Savidis, “Evolving On-Chip Power Delivery through Particle Swarm Optimization,” Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), pp. 1 – 6, September 2019.
  18. R. Kuttappa, B. Taskin, S. Lerner, V. Pano, and I. Savidis, “Robust Low Power Clock Synchronization for Multi-Die Systems,” Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 1 – 6, July 2019.
  19. V. V. Rao and I. Savidis, “Mesh Based Obfuscation of Analog Circuit Properties,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1 – 5, May 2019.
  20. K. Juretus and I. Savidis, “Increasing the SAT Attack Resiliency of In-Cone Logic Locking,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1 – 5, May 2019.
  21. M. S. Hossain and I. Savidis, “Reusing Leakage Current for Improved Energy Efficiency of Multi-voltage Systems,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1 – 5, May 2019.
  22. K. Juretus, V. V. Rao, and I. Savidis, “Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies,” Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 483 – 488, May 2019.
  23. M. S. Hossain and I. Savidis, “Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery,” Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)}, pp. 244 – 251, October 2018.
  24. V. V. Rao and I. Savidis, “Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory,” Proceedings of the IEEE International Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 102 – 106, October 2018.
  25. K. Juretus and I. Savidis, “Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security,” Proceedings of the IEEE International Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 366 – 369, October 2018.
  26. D. Werner, K. Juretus, I. Savidis, Mark Hempstead “Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures,” Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 83 – 91, October 2018.
  27. F. Castro, I. Savidis, and A. Sarmiento “A Quasi-Analytic Behavioral Model for the Single-electron Transistor for Hybrid MOS/SET Circuit Simulation,” Proceedings of the IEEE Nanotechnology Materials and Devices Conference (NMDC), pp. 1 – 4, October 2018.
  28. K. Juretus and I. Savidis, “Time Domain Sequential Locking for Increased Security,” Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp. 1 – 5, May 2018.
  29. M. S. Hossain and I. Savidis, “Noise Constrained Optimum Selection of Supply Voltage for IoT Applications,” Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp. 1 – 5, May 2018.
  30. K. Juretus and I. Savidis, “Enhanced Circuit Security Through Hidden State Transitions,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), pp. 781 – 784, March 2018.
  31. V. V. Rao and I. Savidis, “Security Oriented Analog Circuit Design Using Satisfiability Modulo Theory Based Search Space Exploration,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), pp. 770 – 774, March 2018.
  32. H. Sayadi, D. Pathak, I. Savidis, H. Homayoun, “Power Conversion Efficiency-aware Mapping of Multithreaded Applications on Heterogeneous Architectures: A Comprehensive Parameter Tuning,” Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 70 – 75, January 2018.
  33. M. S. Hossain and I. Savidis, “Bi-directional Input/Output Circuits with Integrated Level Shifters for Near-Threshold Computing,” Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1240 – 1243, August 2017.
  34. I. Daulagala and I. Savidis, “Clock Tree Synthesis for Heterogeneous 3-D Integrated Circuits,” Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), pp. 1 – 6, May 2017.
  35. D. Pathak, H. Homayoun, and I. Savidis, “Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery,” Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 387 – 392, May 2017.
  36. V. V. Rao and I. Savidis, “Protecting Analog Circuits with Parameter Biasing Obfuscation,” Proceedings of the IEEE Latin American Test Symposium (LATS), pp. 1 – 6, March 2017.
  37. J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. Dandekar, “Physical Gate Based Preamble Obfuscation for Securing Wireless Communication,” Proceedings of the International Conference on Computing, Networking and Communications (ICNC), pp. 293-297, Jan. 2017.
  38. K. Siozios, I. Savidis, and D. Soudris, “A Framework for Exploring Alternative Fault-Tolerant Schemes Targeting 3-D Reconfigurable Architectures,” Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS),, pp. 336 – 341, July 2016.
  39. K. Juretus and I. Savidis, “Reducing Logic Encryption Overhead Through Gate Level Key Insertion,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1714 – 1717, May 2016.
  40. M. S. Hossain and I. Savidis, “Robust Near-Threshold Inverter with Improved Performance for Ultra-Low Power Applications,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 738 – 741, May 2016.
  41. D. Pathak, M. Hajkazemi, M. Tavana, H. Homayoun, and I. Savidis, “Energy Efficient On-Chip Power Delivery with Run-Time Voltage Regulator Clustering,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1210 – 1213, May 2016.
  42. K. Juretus and I. Savidis, “Reduced Overhead Gate Level Logic Encryption,” Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), pp. 15 – 20, May 2016.
  43. D. Pathak, M. Hajkazemi, M. Tavana, H. Homayoun, and I. Savidis, “Load Balanced On-Chip Power Delivery for Average Current Demand,” Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), pp. 439 – 444, May 2016.
  44. K. Juretus and I. Savidis, “Low Overhead Gate Level Logic Encryption,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), pp. 455 – 459, March 2016.
  45. M. S. Hossain and I. Savidis, “Dynamic Current Mode Inverter for Ultra-Low Power Near-Threshold Computing,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), pp. 409 – 412, March 2016.
  46. Juretus and I. Savidis, “Securing Integrated Circuits Through Gate-Level Logic Encryption,” 2015 Defense Innovation Summit, pp. 1, December 2015.
  47. M. Tavana, D. Pathak, M. Hajkazemi, I. Savidis, and H. Homayoun, “Realizing Complexity Effective On Chip Power Delivery for Many-Core Platforms by Exploiting Optimized Mapping,” Proceedings of the International Conference on Computer Design, pp. 581-588, October 2015.
  48. M. K. Tavana, M. H. Hajkazemi, D. Pathak, I. Savidis, and H. Homayoun, “ElasticCore: Enabling Dynamic Heterogeneity With Joint Core and Voltage/Frequency Scaling,” Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 1 – 6, June 2015.
  49. D. Pathak and I. Savidis, “Power Supply Voltage Detection and Clamping Circuit for 3-D Integrated Circuits,” Proceedings of the IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference, pp. 1-3, October 2014.
  50. D. Pathak and I. Savidis, “Run-Time Voltage Detection Circuit for 3-D IC Power Delivery,” Proceedings of the IEEE International System-on-Chip (SoC) Conference, pp. 183-187, September 2014.
  51. B. Vaisband, I. Savidis, and E. G. Friedman, “Thermal Conduction Path Analysis in 3-D ICs,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 594-597, June 2014.
  52. I. Savidis and E. G. Friedman, “Thermal Coupling in TSV-Based 3-D Integrated Circuits,” Proceedings of the Workshop on 3-D Integration, Design, Automation & Test in Europe Conference, March 2014.
  53. I. Savidis and E. G. Friedman, “Test Circuits for 3-D Systems Integration,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), pp. 181-184, March 2012.
  54. H. Wu, B. Ciftcioglu , R. Berman, S. Wang, J. Hu, I. Savidis, M. Jain, D. Moore, M. Huang, E. Friedman, and G. Wicks, “Chip-Scale Demonstration of 3-D Integrated Intra-Chip Free-Space Optical Interconnect (Invited Paper),” Photonics West: SPIE Optoelectronic Integrated Circuits XIV, Feb. 2012.
  55. I. Savidis, V. Pavlidis, and E. G. Friedman, “Clock Distribution Models of 3-D Integrated Systems,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) , pp. 2225-2228 May 2011.
  56. I. Savidis, S. Kose, and E. G. Friedman, “Power Grid Noise in TSV-Based 3-D Integrated Systems,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech) , pp. 129-132, March 2011.
  57. B. Ciftcioglu , R. Berman, J. Zhang, Z. Darling, A. Garg, J. Hu, M. Jain, P. Liu, I. Savidis, S. Wang, J. Xue, E. G Friedman, M. Huang, D. Moore, G. Wicks, and H. Wu, “Initial Results of Prototyping a 3-D Integrated Intra-Chip Free-Space Optical Interconnect,” Proceedings of the Workshop on the Interaction between Nanophotonic Devices and Systems (WINDS 2010) , December 2010.
  58. J. Xue, A. Garg, B. Ciftcioglu, J. Hu, S. Wang, I. Savidis, M. Jain, R. Berman, P. Liu, M. Huang, H. Wu, E. Friedman, G. Wicks, and D. Moore, “An Intra-Chip Free-Space Optical Interconnect,” Proceedings of the Annual International Symposium on Computer Architecture (ISCA) , pp. 94-105, June 2010.
  59. B. Ciftcioglu , R. Berman, J. Zhang, Z. Darling, S. Wang, J. Hu, J. Xue, A. Garg, M. Jain, I. Savidis, D. Moore, M. Huang, E. G Friedman, G. Wicks, and H. Wu, “3-D Integrated Intra-Chip Free-Space Optical Interconnect,” Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC) Student Research Forum, February 2010.
  60. J. Xue, A. Garg, B. Ciftcioglu, S. Wang, I. Savidis, J. Hu, M. Jain, M. Huang, H. Wu, E. G. Friedman, G. W. Wicks, and D. Moore, “An Intra-Chip Free-Space Optical Interconnect,” Proceedings of the 3rd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI ‘ 09) held in conjunction with the 36 th International Symposium on Computer Architecture , June 2009.
  61. I. Savidis, E. G. Friedman, V. F. Pavlidis, and G. De Micheli, “Clock and Power Distribution Networks for 3-D Integrated Circuits,” Proceedings of the Workshop on 3D Integration, Design, Automation & Test in Europe Conference, March 2009.
  62. I. Savidis, S. M. Alam, A. Jain, S. Pozder , R. E. Jones, and R. Chatterjee, “Electrical Modeling and Characterization of Through-Silicon vias (TSVs) for 3-D Integrated Circuits,” Proceedings of VLSI/ULSI Multilevel Interconnect Conference (VMIC) , pp. 181-186, Oct. 2008.
  63. V. F. Pavlidis, I. Savidis, E. G. Friedman, “Clock Distribution Architectures for 3-D SOI Integrated Circuits,” Proceedings of the IEEE International SOI Conference, pp. 111-112, October 2008.
  64. V. F. Pavlidis, I. Savidis, E. G. Friedman, “Clock Distribution Networks for 3-D Integrated Circuits,” Proceedings of the IEEE Custom Integrated Circuits Conference , pp. 651-654, September 2008.
  65. I. Savidis and Eby G. Friedman, “Electrical Modeling and Characterization of 3-D Vias,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) , pp. 784-787, May 2008.
  66. I. Savidis, A. Jukna, and R. Sobolewski, “Contactless Determination of Tc in Very Small Single Crystal MgB 2 and Thin Film YBCO,” IEEE Student Paper Contest SoutheastCon 2004 , March 2004.
  67. I. Savidis, and R. Sobolewski, “Characterization of Josephson Junctions,” University of Rochester Journal , August 2000.

Workshop Presentations

  1. I. Vaisband, S. Kose, I. Savidis, and E. G. Friedman, “On-Chip Power Delivery,” CEIS University Technology Showcase, Rochester, New York, April 6, 2011.
  2. I. Savidis and E. G. Friedman, “Clock Distribution Topologies for 3-D Integrated Circuits,” CEIS University Technology Showcase, Rochester, New York, February 12, 2009.
  3. V. F. Pavlidis, I. Savidis, and E. G. Friedman, “Clock Distribution Networks for 3-D Integrated Circuits,” Massachusetts Institute of Technology Lincoln Laboratory’s 3-D Integrated Circuit Multi-Project Wafer Review, Boston, Massachusetts, September 15, 2008.
  4. I. Savidis and E. G. Friedman, “Electrical Modeling and Characterization of 3-D Vias,” IEEE International Symposium on Circuits and Systems (ISCAS) Best Paper Award Contest , May 2008.

Conference Presenter

  1. Presented “Clock Distribution Models of 3-D Integrated Systems,” at the IEEE International Symposium on Circuits and Systems (ISCAS) , May 2011.
  2. Presented “Power Grid Noise in TSV-Based 3-D Integrated Systems,” at the Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech) , March 2011.
  3. Presented “Clock Distribution and Power Delivery for 3-D Integrated Circuits,” at the Integrated Circuit Design Meeting (internal), January 2009.
  4. Presented “Clock Distribution Architectures for 3-D SOI Integrated Circuits,” at the IEEE International SOI Conference, pp. 111-112, October 2008.
  5. Presented “Electrical Modeling and Characterization of 3-D Vias,” at the IEEE International Symposium on Circuits and Systems (ISCAS) , May 2008.
  6. •  Presented “Clock and Power Distribution Networks for Three-Dimensional Circuits: Preliminary Design Review,” at the Integrated Circuits Design Meeting (internal), October 2006.
  7. Presented “Contactless Determination of T c in Very Small Single Crystal MgB 2 and Thin Film YBCO,” at the IEEE Student Paper Contest SoutheastCon 2004 , March 2004.

Technical Industrial Presentations

  1. Presented various bi-weekly update reports to Cisco Systems, Inc. for “3-D Test Circuit on Power Delivery,” Award number: 056165-002, May 2012 – August 2012.
  2. Presented “Recent Research in 3-D Circuit Design and Related Test Circuits,” to Qualcomm Research October 2011.
  3. Presented “Recent Research in 3-D Circuit Design and Related Test Circuits,” to Samsung Research September 2011.
  4. Presented “Lessons Learned in 3-D Verification,” to Kodak Research, Kodak Park, Rochester, NY, October 2008.