Kyle Juretus

Ioannis Savidis

Kyle is a Ph.D. student working in VLSI circuit design with a focus in hardware security. His research interests include circuit level techniques to prevent intellectual property theft and counterfeiting, mitigating side-channel leakage of integrated circuit designs, and design automation for hardware security. Kyle is currently an NDSEG fellow and received Bachelor of Science degrees in both Computer Engineering and Electrical Engineering from Drexel University in 2014.

Publications:

Journal Publications:

[J2] K. Juretus and I. Savidis, “Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. PP, No. PP, pp. 1- 14, June 2019.

[J1] J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. R. Dandekar, “Securing Wireless Communication via Hardware-Based Packet Obfuscation,” Journal of Hardware and Systems Security, Vol. 3, No. 3, pp. 261–272, May 2019.

Conference Publications:

[C10] K. Juretus and I. Savidis, “Increasing the SAT Attack Resiliency of In-Cone Logic Locking,” Proceedings of the International Symposium on Circuits and Systems, pp. 1 – 5, May 2019.

[C9] K. Juretus, V. Rao, and I. Savidis, “Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies,” Proceedings of the IEEE/ACM International Great Lakes Symposium on VLSI, pp. 483-488, May 2019.

[C8] K. Juretus and I. Savidis, “Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security,” Proceedings of the IEEE International Asia Pacific Conference on Circuits and Systems, pp. 366 – 369, October 2018.

[C7] D. Werner, K. Juretus, I. Savidis, Mark Hempstead, “Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures,” Proceedings of the IEEE International Conference on Computer Design, pp. 83 – 91, October 2018.

[C6] K. Juretus and I. Savidis, “Time Domain Sequential Locking for Increased Security,” Proceedings of the International Symposium on Circuits and Systems, pp. 1 – 5, May 2018.

[C5] K. Juretus and I. Savidis, “Enhanced Circuit Security Through Hidden State Transitions,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference, pp. 781 – 784, March 2018.

[C4] J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. Dandekar, “Physical Gate Based Preamble Obfuscation for Securing Wireless Communication,” Proceedings of the International Conference on Computing, Networking and Communications, pp. 293-297, January 2017.

[C3] K. Juretus and I. Savidis, “Reducing logic encryption overhead through gate level key insertion,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1747-1717, May 2016.

[C2] K. Juretus and I. Savidis, “Reduced Overhead Gate Level Logic Encryption,” Proceedings of the IEEE/ACM International Great Lakes Symposium on VLSI, pp. 15-20, May 2016.

[C1] K. Juretus and I. Savidis, “Low Overhead Gate Level Logic Encryption,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference, pp. 455 – 459, March 2016.

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Patents:

[P7] K. Juretus, V. Rao, and I. Savidis, “Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies,” US Patent Application No. 62,839,858.

[P6] K. Juretus and I. Savidis, “Increasing the Resiliency of In-Cone Logic Locking Against the SAT Attack Through Maximum Fanout Free Cones,” US Patent Application No. 62,798,282.

[P5] J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. Dandekar, “Physical Layer Key Based Interleaving for Secure Wireless Communication,” US Patent Application No. 62,515,369.

[P4] J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. Dandekar,  “Physical Layer Key Based Pilot Encryption for Secure Wireless Communication,” US Patent Application No. 62,517,359.

[P3] V. Rao, I. Savidis, and K. Juretus, “Protecting Analog Circuits with Parameter Biasing Obfuscation,” US Patent Application No. 15,918,278.

[P2] J. Chacko, K. Juretus, M. Jacovic, C. Sahin, N. Kandasamy, I. Savidis, and K. Dandekar, “Physical Gate Based Preamble Obfuscation for Securing Wireless Communication,” US Patent Application No. 18,132,796.

[P1] K. Juretus and I. Savidis, “Low Overhead Gate Level Logic Encryption,” US Patent Application No. 62,245,155.

Academic Services:

  • Reviewer for IEEE Transactions on Very Large Scale Integration  Systems (TVLSI)
  • Reviewer for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  • Reviewer for Microelectronics Journal (MEJ)
  • Reviewer for IEEE International Symposium on Circuits and Systems (ISCAS), 2017 – 2019
  • Reviewer for IEEE Great Lakes VLSI Symposium (GLSVLSI), 2016 – 2019
  • Reviewer for IEEE/ACM International Conference On Computer Aided Design (ICCAD) 2018
  • Reviewer for IEEE/ACM Design Automation Conference (DAC) 2018 and 2019
  • Reviewer for IEEE International Conference on Computer Design (ICCD) 2018 and 2019
  • Reviewer for IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2018 and 2019