Skip to main content
Drexel ICE
  • Research
    • 3D Integrated Circuits
      • TSV Modeling and Characterization
      • Synchronization in 3-D Integrated Circuits
      • Clock Tree Synthesis (CTS) for 3-D Integrated Circuits
      • 3-D Integrated Circuit Power Delivery
      • On-Chip Power Delivery with Run-Time Voltage Regulator Clustering for 3-D and 2-D ICs
      • 3-D Integrated Free-Space Optical Interconnect for Multi-Core Systems
      • Thermal Modeling and Mitigation
    • Hardware Security
      • Run-time Detection and Countermeasures
      • Attack Prevention Through Design for Trust Algorithms and Methodologies
    • Sub/Near-Threshold Circuits with Current-Mode Logic
      • Power Reduction using NTC with CML
  • Members
  • News
  • Publications
    • Dissertation
    • Book Chapter
    • Journal Papers
    • Conference Papers
    • Workshop Presentations
    • Conference Presenter
    • Technical Industrial Presentations
  • Contact

Month: October 2014

Paper presented at the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

October 9, 2014April 11, 2016 Divy Pathak

The paper titled “Power Supply Voltage Detection and Clamping Circuit for 3-D Integrated Circuits” was presented at the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), held in Milbrae, California from October 06-09, 2014.

Recent Posts

  • Two Papers Presented at ISCAS 2019
  • Prof. Ioannis Savidis Awarded 2018 NSF CAREER Award
  • The Joseph and Shirley Carleone Endowed Fellowship is awarded to Divy Pathak for the academic year 2017-2018.
  • Two Papers Presented at GOMACTech 2018
  • Prof. Ioannis Savidis Wins IEEE Philadelphia Section Award

Archives

  • May 2019
  • June 2018
  • May 2018
  • March 2018
  • June 2017
  • March 2017
  • February 2017
  • May 2016
  • April 2016
  • March 2016
  • October 2015
  • July 2015
  • April 2015
  • October 2014
  • September 2014
Drexel ICE All rights reserved. Theme by Colorlib Powered by WordPress