Prof. Ioannis Savidis has been awarded a prestigious NSF CAREER Award for “Parameter Obfuscation: A Novel Methodology for the Protection of Analog Intellectual Property.”
Author: Ioannis Savidis
Two Papers Presented at GOMACTech 2018
Prof. Ioannis Savidis presented two ICE Lab papers at the Government Microcircuit Applications & Critical Technology Conference in Miami, Florida held on March 12-14, 2018:
1) Kyle Juretus and Ioannis Savidis, “Enhanced Circuit Security Through Hidden State Transitions.”
Abstract: A technique is developed that uses the state space of an integrated circuit (IC) to increase security. Timing path dependencies and coupling capacitance are utilized to create hidden state transitions that are not observable after netlist extraction. Temporal based transitions are also introduced to shift key dependencies into the time domain. The state space dependencies of the IC serve as a means to counter the SAT attack. Implementing temporal based transitions increases the area of the circuit by 68.42%, the power by 43.17%, and does not impact circuit delay. However, an increased circuit size significantly reduces the overhead of implementing state space encryption. For example, encrypting two registers in the s15850 ISCAS89 benchmark circuit resulted in an area overhead of 0.026%, providing a means to secure sequential logic with minimal overhead.
2) Vaibhav Venugopal Rao and Ioannis Savidis, “Dynamic Current Mode Inverter for Ultra-Low Power Near-Threshold Computing.”
Abstract: A technique to enhance the security of analog circuits using Satisfiability Modulo Theory (SMT) based design space exploration is described. The analog satisfiability (aSAT) technique takes as inputs generic circuit equations and performance constraints and, by exhaustively exploring the design space, outputs transistor sizes that satisfy the given constraints. The aSAT methodology is applied to parameter biasing obfuscation, where the width and length of a transistor are obfuscated to mask circuit properties. The proposed methodology was used in the design of a differential amplifier and an operational amplifier, where the widths and lengths determined through aSAT analysis were shown to meet the target circuit specifications. For the operational amplifier, transistor dimensions determined through aSAT analysis for a set of performance constraints were characterized and were found to meet the performance targets, however, there was a 7 MHz reduction in the gain bandwidth product. e simulated results indicate that the developed design methodology achieves a fast and accurate determination of transistor sizes for target specications.
Prof. Ioannis Savidis Wins IEEE Philadelphia Section Award
Prof. Ioannis Savidis wins the 2018 IEEE Philadelphia Section Delaware Valley Young Electrical Engineer of the Year Award.
Citation: “For contributions in hardware security and trust. Specifically, for the obfuscation of digital and analog circuits through novel algorithms and methodologies that secure intellectual property from reverse engineering, cloning, and counterfeiting.”
Papers Presented at GLSVLSI 2016
Kyle Juretus presented “Reduced Overhead Gate Level Logic Encryption” and Prof. Ioannis Savidis presented “Load Balanced On-Chip Power Delivery for Average Current Demand” at the 2016 Great Lakes Symposium on Very Large Scale Integration (GLSVLSI).
Divy Pathak wins conference travel awards
Divy Pathak is awarded the 2016 IEEE Circuits and Systems Society Student Travel Award and the International Travel Award from Drexel University to present her paper at ISCAS 2016 in Montreal, Canada.
Kyle Juretus Awarded Student Fellowship
Kyle Juretus, a second year Ph.D. student working in my laboratory, was awarded both a Science, Mathematics and Research for Transformation (SMART) Defense Scholarship through the American Society for Engineering Education and a National Defense Science and Engineering Graduate (NDSEG) Fellowship.
Papers Presented at GOMACTech 2016
Two ICE Lab papers were presented at the Government Microcircuit Applications & Critical Technology Conference in Orlando Florida held on March 14-17, 2016:
1) Kyle Juretus and Ioannis Savidis, “Low Overhead Gate Level Logic Encryption.”
Abstract: Untrusted third-parties in the IC design flow have raised serious security and reliability concerns. An area of research aimed at ensuring secure and reliable ICs for critical applications is logic encryption, however current implementations incur high per-gate overheads. This paper focuses on gate level logic encryption, with the goal of substantially reducing the per-gate overhead of implementing the encrypted logic.
2) Shazzad Hossain and Ioannis Savidis, “Dynamic Current Mode Inverter for Ultra-Low Power Near-Threshold Computing.”
Abstract: Near-threshold computing (NTC) is a promising technique for low power computation with improved performance per watt. In this paper, three novel differential inverters are proposed that operating at near-threshold voltages. Characterization of the proposed inverters indicates improvements over CMOS and CML with regard to power, performance, and robustness, with a minor cost in area.